/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

`include "defines.v"

module pc_reg(
    input  wire     clk,
    input  wire     rst,
    input  wire[5:0]	    stall,

    input  wire	            branch_flag_i,
    input  wire[`RegBus]    branch_target_address_i,

    output reg[`InstAddrBus] pc,
    output reg      ce
);

  always @ (posedge clk) begin
    if (rst == `RstEnable) begin
      ce <= `ChipDisable;	// Inst memory disable
    end else begin
      ce <= `ChipEnable;	// Inst memory enable
    end
  end

  always @ (posedge clk) begin
    if (ce == `ChipDisable) begin
      pc <= 32'h00000000;
    end else if (branch_flag_i == `Branch) begin
      pc <= branch_target_address_i;
    end else if(stall[0] == `Stop) begin
      pc <= pc;
    end else begin
      pc <= pc + 4'h4;		// Send to Inst memory and if_id regs
    end
  end

endmodule
